The invention relates to a connection arrangement of at least one electric and/or electronic component comprising a join partner, composite element and a method for configuring the connection arrangement.
In many areas of technology, electronic components, such as, e.g., integrated circuits (IC), transistors or diodes are used within electrical circuit arrangements. A variety of electronic components are hereby fixed to a base part, e.g. substrate or something similar. The electronic components are fixed, for example, to the base part by means of a connection layer, such as, e.g., an adhesive, solder or sintered layer. Due to the difference between ambient, joining and operating temperature, the rigidity of the connection layer and the distinctly different expansion coefficients of, for example, IC and substrate, very high mechanical or thermomechanical stresses can however occur in the electronic components. As a result, thermal stresses can lead to a so-called “clam-shell marked fracture” on the electronic component, wherein partial regions of the surface of the electronic component have broken away. This can lead to a very short service life of such electronic assemblies.
In order to reduce the occurrence of mechanical stresses within the electronic component, it is known to introduce round depressions, so-called dimples, into the substrate surface around the region of the fixed electronic component. The substrate is now more elastic in this region on account of the round depressions; thus enabling mechanical stresses resulting from differing expansion coefficients of the substrate, the connection layer and the electronic component to already be broken down in the region of the substrate enclosed by the round depressions.
The introduction of the dimples entails an additional manufacturing step in providing the substrate.
An arrangement of a semiconductor chip on a metal substrate is known from the first publication of the American patent application US 2010/0187678 A1. The semiconductor chip is thereby attached to the metal substrate at low pressure by means of sintering a silver paste. In addition, the semiconductor chip has bonded connections which connect said semiconductor chip to contacting points. The arrangement previously described together with the bonded connections is completely coated from the outside with a metal oxide coating (SnO, AlO). The arrangement coated in this manner is furthermore encapsulated by a polymer material. The metal oxide coating achieves a stress reduction for the semiconductor chip. Such a coating is expensive because it must be applied to the entire arrangement. Furthermore, the application of the coating to the arrangement as a spatial entity is difficult and entails effort and expense. In addition, only methods can be used in which regions adjacent to the arrangement can be omitted from such a coating.